Apparatus for obtaining a substantially continuously scaled analogue representing the average value of a sequence of binary words

ABSTRACT

Apparatus for obtaining a substantially continuously scaled analogue representing the average value of a sequence of binary words, comprising an accumulator for storing the sequence, a digital to analogue converter, a multiplexer to supply the accumulator sum to the converter, a counter for registering the number of words supplied to the accumulator and logic circuit means driven by the counter and adapted to set the multiplexer in position for the supply to the converter of the quotient of the accumulator word sum and the number of words counted by the counter and to afford at the converter a reference voltage proportional to the quotient, the converter by multiplying the voltage reference and quotient providing the output which is an average word.

United States Patent 91 Hodge et a].

[45] Nov. 13, 1973 APPARATUS FOR OBTAINING A SUBSTANTIALLY CONTINUOUSLYSCALED ANALOGUE. REPRESENTING THE AVERAGE VALUE OF A SEQUENCE OF BINARYWORDS [76] Inventors: Stephen Raymond Hodge; David Thompson Argent, bothof Easthouses Rd., Newton Grange, Midlothian, Scotland 22 Filed: Oct.10, 1972 21 Appl. No.: 295,876

[52] US. Cl. 235/150.5

[51] Int. Cl. G06g 7/16, G06j 1/00 [58] Field of Search 235/150.5, 164,156, 235/l50.52

[56] References Cited UNITED STATES PATENTS 3,462,590 8/1969 Jenkins235/l50.5 3,431,405 3/1969 Dawson 235/l50.5

3,484,589 12/1969 Jernakofi 235/l50.5

Primary Examiner-Gareth D. Shaw AttorneyAlbin Browdy et al.

[5 7] ABSTRACT Apparatus for obtaining a substantially continuouslyscaled analogue representing the average value of a sequence of binarywords, comprising an accumulator for storing the sequence, a digital toanalogue converter, a multiplexer to supply the accumulator sum to theconverter, a counter for registering the number of words supplied to theaccumulator and logic circuit means driven by the counter and adapted toset the multiplexer in position for the supply to the converter of thequotient of the accumulator word sum and the number of words counted bythe counter and to afford at the converter a reference voltageproportional to the quotient, the converter by multiplying the voltagereference and quotient providing the output which is an average word.

2 Claims, 2 Drawing Figures ANALOGUE OUTPUT a /2amA SHEET 10F 2 2 FIG].

ANALOGUE OUTPUT 2 1- 1 6' 2/28 64 32%15 a 4 2 25 x KQKD mum m K0 K1? m 4I4 I l5 22 7 W 20 1791 J27 'the multiplexer means being settable in anumber, n, of

positions in each of which it is arranged for the supply to theconverter of the quotient of the accumulator word sum to a predeterminedsignificant bit and 2", a counter for registering the number of wordssupplied to the accumulator and having a capacity of registering up to2" words, and logic circuit means driven by the counter and adapted toset the multiplexer in position for the supply to the converter of thequotient of the accumulator word sum to said predetermined significantbit and 2" and to afford at the converter a reference voltageproportional to the quotient of 2" and the number of words counted bythe counter, the converter by multiplying the voltage reference andmultiplexer input thereto providing an output which is the average word.

The invention will now be described by way of example with reference tothe accompanying drawings, in which:

FIG. 1 is a circuit diagram largely in block form of an apparatus inaccordance with the invention; and

FIG. 2 is a table summarising the operation of the circuit of FlG. 1 ateach of 40 successive counts.

Referring first to FIG. 1, the apparatus consists of a 16-bitaccumulator l for storing the sum of a sequence of words suppliedthereto in binary form. Nine consecutive bits of the accumulator areindexed at any one time by a nine nine way multiplexer 2, the output ofwhich is fed into a digital to analogue converter 3. The converter 3 isof known form per se and is fed, in addition to the output from themultiplexer, with a reference voltage which is generated in a voltagefollower 4 from a Norton circuit 40 involving a constant current source13, in parallel with which are each of resistors 5-12, the values ofwhich from resistor 5-12 increase in binary sequence resistor 5 being 1Kfland resistor 12, 128 KO. Resistors 6-12 are switched across thesource 13 by respective switches 14-20. The switches 14-20 and themultiplexer switches are controlled by logic circuit means 21 in theform of a combinational network which is driven from an eight-bit scancounter 22,

I which counts the number of words supplied to the accumulator.

The logic circuit means 21 consist of two distinct sections, a firstsection providing the control logic driving the nine by eight waymultiplexer 2 and a second sec- 128 or 256. The switch from 1 to 0 ofthe output of the combinational logic serves as the clock input to athreebit binary counter consisting of three flip-flops, a fourthflip-flop being provided and being set when the scan counter incrementsfrom 1 to 2 and remaining set for the rest of the count. The four-bitnumber thus obtained is used as a binary address to the multiplexer 2 toswitch the latter and thus determine the selection of the word from theaccumulator l.

The second section of logic consists of combinational logic of the samegeneral composition as that of the first section, i.e., mainly groups ofexclusive -OR and NOR functions, which examines the logic levels of theelements, which are flip-flops, of the counter 22 to produce therefromthe necessary switching functions for the switches 14 to 20.

It will be seen that the logic circuit means 21 set the multiplexer inany one of n positions where n has the maximum value of nine and thatthe multiplexer accordingly supplies to the digital to analogueconverter 3 the quotient of the word sum in the accumulator to the ninthmost significant bit and 2".

The voltage reference input from the voltage follower 4 to the converteris proportional to the quotient of 2" and the number of words insertedinto the accumulator, n having the value of the setting of themultiplexer at the particular total of words inserted into theaccumulator.

The table of FIG. 2 illustrates the operation of the switches 14-20 forthe first forty words introduced into the accumulator. To explain thetable fully, one typical example is worked as follows: at theseventeenth word, switches 14-17 are open and switches 18-20 are closed.Thus the parallel resistance (R across the source 13 equals 128/135 chmswhich, multiplied by the current from the source of 1 and 127/128milliamperes gives a reference voltage (V of 1.89 volts. As themultiplexer is in position No. 6 when the seventeenth word isintroduced, the multiplexer serves to divide the word total in theaccumulator by 2 i.e., 32. As the reference voltage is multiplying themultiplexer input to the converter, the nett division effected by theconverter is 32/1.89 equals 16.94," which is closely approximate to 17.

It will be apparent therefore that each time a new binary number of upto eight digits is put into the accumulator, the counter 22 clocks upone count and so registers the total number of words in the accumulator.The logic 21, driven by the counter 22, causes the voltage follower toproduce a reference voltage of a value between 1.00 and 1.992 volts andfurther causes appropriate setting of the multiplexer. As the digital toanalogue converter multiplies the two inputs thereto, it provides anoutput which is almost exactly proportional to the content of theaccumulator divided by the number of words accumulated therein.

Whilst the apparatus has been described in relation to a sixteen-bitaccumulator and a counter which counts up to 256 words, the apparatuscan be adapted novel means of ensuring that the analogue equivalent ofthe average of a sequence of numbers entered into an accumulator isalways generated with approximately the correct scaling factor.

We claim:

1. Apparatus for obtaining a substantially continuously scaled analoguesignal representing the average value of a sequence of binary words,comprising an accumulator for storing the sum of a sequence of wordssupplied thereto in binary form, a digital to analogue converter,multiplexer means for supplying the accumulator word sum to theconverter, the multiplexer means being settable in a number, n, ofpositions in each of which it is arranged for the supply to theconverter of the quotient of the accumulator word sum to a predeterminedsignificant bit and 2", a counter for registering the number of wordssupplied to the accumulator and having a capacity of registering up to2" words, and logic circuit means driven by the counter and adapted toset the multiplexer in position for the supply to the converter of thequotient of the accumulator word sum to said predetermined significantbit and 2" and to afford at the converter a reference voltageproportional to the quotient of 2" and the number of words counted bythe counter, the converter by multiplying the voltage reference andmultiplexer input thereto providing an output which is the average word.

2. Apparatus as claimed in claim 1, further including a Norton circuit,wherein the logic circuit operates said Norton circuit to afford at theconverter the reference voltage.

1. Apparatus for obtaining a substantially continuously scaled analoguesignal representing the average value of a sequence of binary words,comprising an accumulator for storing the sum of a sequence of wordssupplied thereto in binary form, a digital to analogue converter,multiplexer means for supplying the accumulator word sum to theconverter, the multiplexer means being settable in a number, n, ofpositions in each of which it is arranged for the supply to theconverter of the quotient of the accumulator word sum to a predeterminedsignificant bit and 2n, a counter for registering the number of wordssupplied to the accumulator and having a capacity of registering up to2n words, and logic circuit means driven by the counter and adapted toset the multiplexer in position for the supply to the converter of thequotient of the accumulator word sum to said predetermined significantbit and 2n and to afford at the converter a reference voltageproportional to the quotient of 2n and the number of words counted bythe counter, the converter by multiplying the voltage reference andmultiplexer input thereto providing an output which is the average word.2. Apparatus as claimed in claim 1, further including a Norton circuit,wherein the logic circuit operates said Norton circuit to afford at theconverter the reference voltage.